In accordance with an aspect of the invention, an analog/multi-level memory array is programmed with threshold voltages Vts that are a non-linear or random function of input voltages such that analog input voltages to the array have a non-linear correspondence with the threshold voltages of memory cells in the memory or conversion array. Applying an analog input voltage signal to the memory array causes memory cells with a lower threshold voltage than the analog input voltage to conduct. By determining which memory cells conduct and which do not conduct, a converted digital representation of the input signal can be obtained. This digital signal is then used to select a corresponding reference cell in another memory or conversion array. The threshold voltage of the selected reference is read, which corresponds to the desired conversion to analog. By applying the converted analog voltage to an analog/multi-level memory array which contains memory cells programmed with the inverse of the conversion, the format of the original signal can then be obtained.
FIG. 4 shows a system 400 for converting an analog signal Ain to a non-linear analog signal Aout using a non-volatile analog/multi-level memory array 410. System 400 includes an analog-to-digital converter (ADC) 420 and a digital-to-analog converter (DAC) 430 that utilizes memory array 410. ADC 420 converts input analog signal Ain to a digital output signal D. DAC 430 then converts digital signal D to a desired analog signal Aout by reading the threshold voltage of the memory cell in the array 410 that corresponds to the digital signal D. The magnitudes of Ain and Aout are not necessarily the same. For example, Aout can be a non-linear representation of Ain, such as according to μ-law or A-law compression characteristics, high-level voltage shifting of Ain, or a random conversion of Ain.
FIG. 5 shows an ADC 500 suitable for use as ADC 420 of FIG. 4. ADC 400 includes a non-volatile memory array 510 (sometimes referred to herein as an analog conversion array) that provides programmable references for signal conversions. The analog conversion array, being programmable, allows the user or manufacturer to select or change the type of conversion implemented in the ADC 500 at any time by reprogramming the threshold voltages of the memory cells in the conversion array or table. ADC 500 includes analog conversion array 510 containing reference cells RC0 to RCx with respective threshold voltages VTA0 to VTAx. The number x is equal to 2n -1, where n is the number of bits in an output digital signal D from ADC 500. In FIG. 5, each reference cell RCi, for i between 0 and x, is an N-channel floating gate transistor that is electrically programmed to an associated threshold voltage VTAi, but alternative embodiments use other types of memory cells. Memory cells having electrically programmable threshold voltages permit changing or reprogramming of a conversion as described below, but ROM cells having threshold voltages that are set or fixed during circuit fabrication are also suitable. Reference cells RC0 to RCx have control gates coupled together by a row line to form a row. ADC 500 uses a row of reference cells to facilitate simultaneous application of the same control gate voltage to all reference cells RC0 to RCx. Other array configurations are possible, particularly in embodiments of ADC 500 that do not require simultaneous application of the same control gate voltage to all reference cells. The drains of reference cells RC0 to RCx are coupled to bias and sense circuits 520 and an encoder 530.
During operation of ADC 500, the sources of reference cells RC0 to RCx are grounded, bias and sense circuits 520 bias the drains of reference cells RC0 to RCx at a positive voltage, and the control gates of reference cells RC0 to RCx receive analog input signal Ain to be converted. The reference cells that have threshold voltages lower than the voltage of analog input signal Ain conduct, which causes output binary signals T0 to Tx from sense amplifiers to go high. Encoder 530 determines which of reference cells RC0 to RCx conduct and which do not conduct and, based on that determination, generates digital output signal D.
FIG. 6 shows an illustrative embodiment of an ADC 600 having an analog conversion array 610 for converting an analog input signal Ain to a 3-bit digital output signal D. Array 610 includes seven reference cells RC1 to RC7. Alternatively, as illustrated in FIG. 5, a conversion array for an n-bit data output signal includes 2n reference cells RC0 to RCx that respectively correspond to digital values zero to 2n -1. However, reference cell RC0 is not required if any analog voltage below the threshold voltage of reference cell RC1 is presumed to have value zero.
In ADC 600, bias and sense circuits 620 include drain-coupled p-channel pull-up transistors 627 and n-channel cascoding transistors 626 for biasing reference cells RC1 to RC7 in conversion array 610. Pull-up transistors 627 have drains and gates connected together and sources coupled to a supply voltage Vcc (typically about 5V, 3V, or lower). Each cascading transistor 626 has a gate bias voltage Vbias of about 1.5 volts and serves to connect the drain of an associated reference cell to the drain of an associated pull-up transistor 627. Each pull-up transistor 627 maintains a high voltage on the input terminal of an associated inverter 628 unless an associated reference cell conducts. When a reference cell coupled to the drain of a pull-up transistor 627 conducts, the reference cell pulls down the voltage on the input terminal of the associated inverter 628. Thus, inverters 628 output binary signals T1 to T7 indicating whether respective reference cells RC1 to RC7 conduct.
An encoder 630 generates output signal D from binary signals T1 to T7. For ADC 600, encoder 630 is a thermometer-to-binary encoder that generates a 3-bit digital output signal D indicating which of reference cells RC1 to RC7 conduct. Thermometer-to-binary encoder 630 implements the digital encoding listed in Table 1.
Methods for designing digital logic which implement the encoding of Table 1 are well known.
FIG. 7A illustrates an ADC 700 having a conversion array 610, sense and bias circuits 720, and an encoder 730, which is also suitable for ADC 420 of FIG. 4. For ADC 700, bias and sense circuits 720 sequentially determine the conductivity state of each of reference cells RC1 to RC7 in array 610 while analog input signal Ain is applied to the control gates of reference cells RC1 to RC7. (Again the example of a 3-bit digital output signal is described, but digital output signal D can have any size through appropriate expansion of conversion array 610 and circuits 720 and 730.) For the sequential determination, bias and sense circuits 720 include select circuits 724 and a sense circuit 722. Select circuits 724 include a column decoder that selects a reference cell that an address signal identifies. Such column decoders are well known for memories. When select circuit 724 selects a reference cell, sense circuit 722 determines the conductivity state of the selected reference cell. Encoder 730 generates digital output signal D from a serial signal indicating the conductivity states of the reference cells. Sequentially biasing or testing reference cells in this fashion can significantly reduce the required power and the required circuit area when compared to sensing all of the reference cells in parallel. In particular, ADC 700 requires only a single sense circuit 722 rather instead of 2n sense circuits which operate in parallel to simultaneously determine all of the conductivity states.
In the illustrated embodiment of ADC 700, sense circuit 722 includes transistors 726 and 727 and an inverter 728. Alternatively, ADC 700 could use any other type sense circuit such as those that are well known for memories such as Flash memories. Select circuits 724 select a reference cell according to the address signal and connect the selected reference cell through transistor 726 to the input node of inverter 727. Pull-up transistor 727 pulls up the voltage on the input terminal of inverter 728 unless the selected reference cell conducts. When the selected reference cell conducts, the reference cell pulls down the voltage on the input terminal of inverter 728. Thus, the output signal from inverter 728 indicates whether the currently selected reference cell conducts.
Encoder 730 includes a counter 732 and a multi-bit latch 734. Counter 732 provides the address signal to select circuits 724 in bias and sense circuits 720. For signal conversion, a clock signal causes counter 732 to sequentially count up from zero. When the count in counter 732 crosses the boundary between the addresses of conductive reference cells and the addresses of non-conductive reference cells, a transition in the output signal from inverter 728 causes latch 734 to register the count signal from counter 732. This count signal is the digital output signal D. For example, if that input signal Ain has a voltage at or just above the threshold voltage VT2 of reference cell RC2, input signal Ain should be converted to the digital value two. When this level of signal Ain is applied, reference cells RC1 and RC2 conduct, and reference cells RC3 to RC7 do not conduct. Initially, the count zero selects reference cell RC1. Reference cell RC1 conducts and causes inverter 728 to assert a high signal to latch 734. In the next clock cycle, the count one selects reference cell RC2. The reference cell RC2 conducts and causes inverter 728 to maintain the high signal to latch 734. In the following clock cycle, the count two selects reference cell RC3. Reference cell RC3 does not conduct and therefore causes inverter 728 to drop the signal to latch 734. The transition in the signal to latch 734 causes latch 734 to register the count signal from counter 732. Thus, digital output signal D represents the value two. Counting can continue or be stopped while latch 734 holds the output value.
Embodiments of ADCs that sequentially determine the conductivity of reference cells can be implemented in a variety of ways. For example, counter 732 in ADC 700 can be replaced with circuitry that performs a binary search for the boundary between conducting and non-conducting reference cells. An exemplary binary search starts at a central address (e.g., 4 for a 3-bit value) and increases or decreases the address depending on whether the reference cell at the current address conducts. The step size (e.g., initially 2) for each change in address decreases by half after each step. Such binary searching can reduce the maximum number of clock cycles required to find the output value, from 2n -1 to n.
FIG. 7B illustrates alternative ADC 750 that also has select circuits 724 and sense circuit 722 sequentially select and sense the conductivity states of reference cells RC1 to RC1. ADC 750 differs from ADC 700 in that a counter 738, instead of latch 734, provides digital output signal D. In ADC 750, counters 732 and 738 are initially reset to zero. Counter 732, in response to a clock signal CLK, sequentially counts through the column addresses of array 610 so that select circuits 724 sequentially connect reference cells RC1 to RC7 to sense circuit 722. In particular, at a rising edge of signal CLK, counter 732 increments the address to select circuit 724, and sense circuit 722 connects to the selected reference cell via a transistor 736 and select circuits 724. If the selected reference cell conducts, the selected reference cell pulls down the voltage on the input terminal of inverter 728, and the output signal from inverter 728 is high. Transistor 736 has a gate coupled to signal CLK so that when signal CLK is low, transistor 736 disconnects sense circuit 722 from select circuits 724 and array 610, pull-up transistor 727 pulls up the input voltage to inverter 728, and the output signal from inverter 728 is low. Accordingly, sense circuit 722 generates a pulse for each reference cell RC1 to RC7 that conducts. Counter 738 counts pulses from sense circuit 722 and outputs the resulting count as signal D.
Another alternative ADC has a conversion array including a column of reference cells that are associated with a conversion. Instead of simultaneously applying analog input voltage Ain to all of the reference cells associated with a conversion, the ADC applies signal Ain only to reference cell (or one row of reference cells) at a time. For this embodiment, bias and select circuits include a row decoder to select the reference cell (or row of reference cells) to which signal Ain is applied. A sense circuit couples to the column line of the column associated with the conversion and to an encoder such as described above for FIGS. 7A and 7B.
Once the digital output signal D is obtained, signal D is then supplied to a DAC for conversion back to the analog domain with the desired conversion (e.g., a non-linear A-law or μ-law characteristic, random, or any other conversion).
FIG. 8 illustrates a DAC 800 suitable for use as DAC 430 of FIG. 4. DAC 800 includes a second non-volatile memory array 810 (sometimes referred to herein as a digital conversion array) containing reference cells RC0 to RCx that have been programmed with the appropriate threshold voltages VTD0 to VTDx for implementing the desired conversion. Note that if VTD0 to VTDx are different than VTA0 to VTAX, the converted analog signal Aout will be different than the input analog signal Ain. A read circuit 840 selects one of reference cells RC0 to RCx based on signal D and determines the threshold voltage of the selected reference cell. Reference cells RC0 to RCx are as described above in regard to FIG. 5, but in DAC 800, reference cells RC0 to RCx have sources grounded and drains coupled to select and bias circuits 820 in read circuit 840. For a conversion of the n-bit digital signal D, select circuit 820 interprets digital signal D as an address that identifies the selected reference cell. Read circuit 840 then determines the threshold voltage of the selected reference cell and provides analog output signal Aout at a voltage that is the same as (or alternatively depends on) the threshold voltage of the selected reference cell. Thus, the threshold voltage VTDi is equal to (or alternatively controls or has a one-to-one correspondence with) the voltage of analog output signal Aout, and programming of threshold voltages VTDi controls the conversion that DAC 700 implements.
Read circuit 840 can be any sort of circuit capable of reading a threshold voltage of a memory cell or transistor. However, in the specific embodiment shown in FIG. 8, read circuit 840 includes select and bias circuits 820, a ramp circuit 842, a sense amplifier 844, and a sample-and-hold circuit 848. For a digital-to-analog conversion, select circuit 820 responds to the multi-bit digital signal D from the ADC by: selecting the reference cell having an address corresponding to signal D; biasing the drain of the selected reference cell at a positive voltage, for example, 1 to 1.5 volts; and connecting the drain of the selected reference cell to sense amplifier 844. Ramp circuit 842, which is coupled to the row line of digital conversion array 810, ramps the control gate voltage of the selected reference cells between voltages Aout,min and Aout,max. Sense amplifier 844, which is coupled to the selected reference cell, senses when the selected reference cell transitions between a non-conducting and a conducting state and triggers sample-and-hold circuit 848 upon sensing the transition. In response to sense amplifier 844, sample-and-hold circuit 848 samples the control gate voltage from ramp circuit 842 and provides analog signal Aout with a voltage equal to or having a one-to-one correspondence with the sampled voltage. Thus, after some time delay, analog output signal Aout is about equal to or has a one-to-one correspondence with the threshold voltage of the selected reference cell. The resulting signal Aout, which is the desired transformation of input signal Ain, can be transmitted, stored, or further processed.
Although FIG. 8 shows a specific embodiment of read circuit 840, other types of read circuits that are capable of determining a threshold voltage can be used. U.S. Pat. No. 5,751,635, entitled "READ CIRCUITS FOR ANALOG MEMORY CELLS", U.S. Pat. No. 5,748,534, entitled "FEEDBACK LOOP FOR READING THRESHOLD VOLTAGES", U.S. Pat. No. 5,748,533, entitled "READ CIRCUIT WHICH USES A COARSE-TO-FINE SEARCH WHEN READING THE THRESHOLD VOLTAGE OF A MEMORY CELL", and U.S. patent app. Ser. No. 09/053,716, entitled "HIGH RESOLUTION MULTI-BIT-PER-CELL MEMORY", filed Apr. 1, 1998 describe some other suitable read circuits and are hereby incorporated by reference in their entirety.
In another embodiment of the present invention, an analog-to-analog converter (AAC) 900, shown in FIG. 9A, can be used to perform analog-to-analog conversion with a single memory array 910. AAC 900 performs two conversions, an analog-to-digital conversion followed by a digital-to-analog conversion. Array 910 includes rows 0 to y of reference cells RC00 . . . RC0x, RC10 . . . RC1x, . . . , RCy0 . . . RCyx having respective threshold voltages VT00 . . . VT0x, VT10 . . . VT1x, . . . , VTy0 . . . VTyx. Each row 0 to y has a row line which connects to the control gates of all the memory cells in the row. Reference cells RC00 to RCyx are also arranged into x+1 columns of reference cells RC00 . . . RCy0, RC01 . . . RCy1, . . . , RC0x . . . RCyx, where reference cells in a column have their drains coupled together by a column line corresponding to the column. In FIG. 9A, the sources of all of reference cells RC00 to RCyx are grounded, but alternatively, one or more source lines can connect the sources of reference cells RC00 to RCyx to erase circuits.
In one embodiment of AAC 900, each row 0 to y in memory array 910 is associated with a different conversion between analog and digital signals. For example, in row 0, threshold voltages VT00 to VT0x may define a linear conversion from analog input signal Ain to the digital output signal Dout, and threshold voltages VT10 to VT1x for row 1 may define a non-linear conversion such as a μ-law or A-law compression from digital signal Din or Dout to the desired analog output Aout. A row decoder 912 selects from array 910 a row identified by a row address signal ROWADDR and applies a signal Vrow from a multiplexer 914 to the selected row. ROWADDR is selected from a conversion select signal CSEL, input address signal Din, or the output signal Dout of encoder 930. Multiplexer 914 provides analog input signal Ain or output signal Aout from multiplexer 915 as signal Vrow during an analog-to-digital conversion and provides a signal Vramp from ramp circuit 842 during a digital-to-analog conversion.
To perform an analog-to-analog conversion with AAC 900, an analog-to-digital conversion is first performed. Multiplexer 914 selects analog input signal Ain, and row decoder 912 applies signal Ain to the row line corresponding to the selected conversion. Row decoder 912 biases unselected row lines to a voltage lower than the threshold voltage of any reference cell RC00 to RCyx in array 910 so that none of the reference cells coupled to unselected row lines conduct. Bias circuit 920 biases all of the column lines of array 910 to a positive voltage (typically 1 to 1.5 volts). Sense amplifiers 944 sense which of the column lines of array 910 couple to conductive reference cells, and each sense amplifier 944 asserts a binary signal indicating whether an associated reference cell in the selected row conducts. Encoder 930 generates output digital signal Dout from the binary signals as described above in regard to FIG. 1.
The resulting digital signal Dout is then used as an input to AAC 900 to perform a digital-to-analog conversion on signal Dout. Multiplexer 914 selects the signal from ramp circuit 842 (as discussed above with respect to FIG. 8), and row decoder 912 applies the selected signal from multiplexer 914 to the selected row line. Again, row decoder 912 biases unselected row lines to a voltage lower than the threshold voltage of any reference cell RC00 to RCyx in array 910 so that none of the reference cells coupled to unselected row lines conduct. Selection and bias circuit 920 biases all of the column lines or a selected column line of array 910 to a positive voltage, and each sense amplifier 944 senses whether the attached column line is coupled to a conductive reference cell. To save power, bias circuit 920 biases only the column line having the column address that signal Dout indicates. A multiplexer 946 selects the one of sense amplifiers 944 that is coupled to the column line having the column address that signal Dout identifies and provides the output binary signal from the selected sense amplifier as a trigger signal for sample-and-hold circuit 848. Accordingly, when the conductivity state of the reference cell in the selected row and the selected column changes, sample-and-hold circuit 848 samples the voltage from ramp circuit 842. Sample-and-hold circuit 848 provides the sampled voltage to analog output signal Aout, resulting in the desired analog-to-analog conversion.
In an alternative embodiment of AAC 900, multiple rows of array 910 contain reference cells for a single conversion. Using multiple rows for a conversion allows higher resolution analog signals and more bits in digital signals. In particular, an n-bit conversion requires about 2n reference cells, and if the number of cells in a row is less than 2n, multiple row can be used for the conversion. Array 910 can still contain reference cells for many different types of conversions implemented with corresponding conversion arrays or tables.
For an analog-to-digital conversion using the alternative embodiment of AAC 900, signal CSEL initially has a value that selects one of the rows associated with the desired conversion, and circuit 940 determines the conductivity states of the reference cells in the current row. If all of the reference cells in the selected row conduct or do not conduct, control circuitry (not shown) changes signal CSEL to select another row corresponding to the desired conversion. The control circuit continues to change signal CSEL until a row is found in which some reference cells conduct and others do not conduct or until two rows that are consecutive in the conversion, are found where one row contains only conducting reference cells and the other row contains only non-conducting reference cells. Once signal CSEL selects the appropriate row, encoder 930 determines digital output signal Dout based on signal CSEL and on which reference cells in the selected row conduct. In particular, signal CSEL, which identifies a row, indicates the most significant bits of signal Dout and the conducting reference cells in the selected row indicate the least significant bits of signal Dout.
For a digital-to-analog conversion, signal CSEL selects the conversion (i.e., a set of rows corresponding to the conversion), and the most significant bits of digital signal Dout from the previous analog-to-digital conversion select the rows corresponding to the conversion. Accordingly, as shown in FIG. 9A, a mixer 916 provides to row decoder 912 an address signal ROWADDR having most significant bits from signal CSEL and least significant bits from signal Dout. The least significant bits of digital input signal Dout select which column of array 910 is read to provide analog output signal Aout. In FIG. 9A, the read circuit includes a ramp circuit 842 that multiplexer 914 and row decoder 912 connect to the selected row line.
FIG. 9B illustrates an AAC 950 which is similar to AAC 900 but uses a single sense circuit 722 to reduce circuit area and power consumption. AAC 950 also uses encoding as described above in regard to FIG. 7A. During an analog-to-digital conversion, counter 732 increments through the possible digital values for the digital signal, and signal CSEL identifies a set of the rows associated with the conversion being performed. Accordingly, mixer 916 generates an address signal ADR that is applied to row decoder 912 and a column decoder 922 to sequentially select reference cells corresponding to the conversion. In particular, after a column address to column decoder 922 counts across a row, row decoder 912 changes the row line to which analog input signal Ain is applied. At the dividing point between conductive and non-conductive reference cells, latch 734 registers the count from counter 732 and provides that count as digital output signal Dout.
Signal Dout is then converted to the desired analog format by applying signal Dout back to the input of read circuit 940. Signal CSEL identifies the set of rows corresponding to a conversion, and digital signal Dout identifies a reference cell that corresponds to the digital value. Accordingly, address signal ADR from mixer 916 is a combination of signals Dout and CSEL that selects the reference cell from the set of row signal CSEL identifies. Column decoder 922 connects that reference cell to sense circuit 722 which triggers sample-and-hold circuit 848 when required to provide the desired analog output signal Aout at the level of the threshold voltage of the target reference cell.
The resulting analog signal Aout is not necessarily the same as the input signal Ain. In other words, signal Aout can correspond to a non-linear, high-level shift, low-level shift, or random mapping of input signal Ain. Such conversions of Ain to Aout can be beneficial for a variety of applications. For example, for voice or audio applications, non-linear logarithmic μ-law and A-law compression schemes can improve the quality of audio signal transmissions because such compressions improve the signal-to-noise ratio and lessen the quantization errors of low amplitude voice signals. Proper programming of the threshold voltages in reference cells RC0 to RCx can implement a μ-law or A-law function or any other desired mapping.
A logarithmic mapping, such as μ-law, produces output signals having relatively higher resolution per quantized level for low level signals than for high level signals. The characteristic mapping for μ-law, which is adopted for use with digital carrier transmission systems in North America, is given by ##EQU1## where V is the maximum voltage of the input analog voltage Ain, μ is a constant (μ=255 for the North America standard), and Aout is the compressed output analog voltage. A normalized plot of equation (1) is shown in FIG. 3 (i.e., for V=1 volt, Ain ranges from 0 to 1 volt, and μ=255) . Thus, the reference cells RC0 to RCx can be programmed with the threshold voltages corresponding to the values of Aout for various input voltages Ain according to equation (1) to realize a μ-law compression. In general, the input voltages used to calculate the corresponding Aout voltages are divided up equally, given by
where Ain,min is the minimum voltage of the input signal, Ain,max is the maximum voltage of the input signal, x+1 is the number of reference cells, and i ranges from 0 to x. An illustrative example in Table 2 below lists the input voltages and corresponding output voltages for Ain,min=0 volts, Ain,max=1 volt, x=10 (i.e., 11 reference cells), and μ=255.
Thus, with appropriate threshold voltages programmed into the reference cells of the memory array, an analog-to-analog conversion of an input analog signal Ain to a logarithmically compressed output analog signal Aout can be obtained.
More generally, threshold voltages VTi according to equation (2) below implement a conversion where the value that signal Aout represents is equal to a function F of the voltage of signal Ain.
Generally, over its range, function F should have a single-valued inverse for an invertable conversion. With other types of conversion functions, analog data can be transmitted which has been encrypted according to the conversion defined by the threshold voltages of memory cells in the conversion array. The encrypted signal, which may be quantized into a digital data stream, can then be transmitted securely over public communication channels. Upon receipt at the desired destination, the encrypted signal is decrypted using an inverse of the conversion array. Because the conversion arrays can be programmed with threshold voltages representing a large number of functions and/or random mappings (i.e., a encryption code), the transmitted signal will be extremely difficult to decode if intercepted, resulting in secure communications. Since the encryption code is stored in the floating gate of the memory cells as electrons, deciphering the encryption code through reverse engineering is essentially impossible. Also, since the conversion array or table can be modified to change the encryption at any time by remote means, such as over phone lines with programming capabilities, secure transmission is virtually guaranteed. For example, the encryption code can be changed just prior to any transmission where security is desired so that knowledge of the prior encryption code is rendered useless.
Threshold voltages for implementing desired conversions can be programmed in analog/multi-level memory arrays, such as described in commonly-owned U.S. Pat. No. 5,694,356, entitled "HIGH RESOLUTION ANALOG STORAGE EPROM AND FLASH EPROM", U.S. Pat. No. 5,680,341, entitled "PIPELINED RECORD AND PLAYBACK FOR ANALOG NON-VOLATILE MEMORY", and U.S. Pat. No. 5,818,757, entitled "ANALOG AND MULTI-LEVEL MEMORY WITH REDUCED PROGRAM DISTURB", and in commonly-owned U.S. patent app. Ser. No. 08/781,741, entitled "SOURCE BIASING IN NON-VOLATILE MEMORY HAVING ROW-BASED SECTORS" and U.S. patent app. Ser. No. 08/889,111, entitled "MULTIPLE ARRAY ARCHITECTURE FOR ANALOG OR MULTILEVEL MEMORY", all of which are incorporated by reference in their entirety.
Once Aout has been converted to the selected format, Aout can be further processed as desired. For example, Aout can be stored in a memory (recording) and read out at a later time (playback), as shown in FIG. 10A. Input analog signal Ain is converted to a logarithmic (or any other desired conversion) analog output signal Aout by an analog-to-analog converter 1000, such as described above. Signal Aout is then stored in an analog/multi-level memory 1010, such as those described in the references above.
Analog signal Aout is stored into analog/multi-level memory 1010 via an analog write circuit 1020, such as described in commonly-owned U.S. Pat. No. 5,687,115, entitled "WRITE CIRCUITS FOR ANALOG MEMORY", which is incorporated by reference in its entirety. Analog write circuit 1020, for example, includes a high voltage shifter for generating a write voltage Vpp corresponding to a shifted voltage of analog signal Aout. Voltage Vpp is applied to the control gate of a selected memory cell in analog/multi-level memory 1010 to raise the threshold voltage of the memory cell. A voltage Vvfy, representing the voltage of Aout, is then applied to the selected memory cell to read or verify the threshold voltage of the memory cell. If the memory cell conducts, indicating a threshold voltage lower than Vvfy, then another write cycle is performed to increase the memory cell's threshold voltage. However, if the memory cell does not conduct, indicating that the threshold voltage is at or above Vvfy, then further writing to the memory cell is stopped, resulting in the selected memory cell being programmed with the voltage of Aout. Write and verify cycles are continued until Aout is properly programmed into analog/multi-level memory array 1010. The converted or compressed analog signal Aout can then be stored in memory array 1010 for later playback.
Upon playback, the threshold voltages of memory cells in array 1010 are read by an analog read circuit 1030. Examples of suitable read circuits are described in commonly-owned U.S. Pat. No. 5,751,635, entitled "READ CIRCUITS FOR ANALOG MEMORY CELLS", which is incorporated by reference in its entirety. One type of read circuit 1030 slowly changes or ramps a control gate voltage asserted to a selected memory cell and then samples and holds the control gate voltage when the selected memory cell first conducts. The sampled control gate voltage is equal to or has a one-to-one correspondence with the threshold voltage of the selected memory cell, which is equal to or can be converted to the analog signal stored in the memory cell. The stored analog signal Aout' is then converted back to the analog signal format of the original signal Ain by an inverse analog-to-analog converter 1040. Converter 1040 utilizes circuits and methods similar to those described above, with the exception that the memory array in converter 1040 implements the inverse function of the original conversion, i.e., the memory cells forming the array are programmed with threshold voltages that are the inverse of the threshold voltages of the memory cells in the original conversion array. As a result, the output of converter 1040, Ain', is a reconstructed analog signal of Ain, where signal Ain' is in the same format as Ain. For example, converter 1040 acts to decipher signal Aout' after encryption in converter 1000, as shown in FIG. 10B. Thus, after encryption, the analog signal Aout, such as a voice signal, can be transmitted securely until reaching its desired destination, such as a deciphering device with a built-in inverse analog-to-analog converter 1040. Upon applying the inverse conversion, signal Aout is deciphered or converted back to its original format.
In another embodiment of an AAC, shown in FIG. 11, a memory system 1100 includes a conversion array 1110 having both analog-to-digital and digital-to-analog conversion and a storage or memory array 1120 within a single larger memory array 1130. In an exemplary embodiment of memory system 1100, array 1130 is a conventional Flash memory array including erasable sectors of memory cells. Preferably, memory cells in either array are erasable without affecting the contents of the other array. Conversion array 1110, for example, as described above with respect to FIGS. 9A and 9B, contains one or more rows of memory cells where each row contains reference cells with threshold voltages programmed for a conversion corresponding to the row. Typically, the content of conversion array 1110 is fixed or is changed less often than the content of storage array 1120.
Connected to array 1130 are a column decoder 1140 and a row decoder 1150. Such column and row decoders are well known in conventional memory systems and select column and row lines as required to access particular memory cells. A ramp or row line bias circuit 842 generates the signal that row decoder 1150 applies to a selected row line when reading the threshold voltage of a selected memory cell on the selected row line. Column decoder 1140 includes bias circuits and control circuits that apply voltages to column lines as required for erase, programming, and read operations, which are not shown for ease of illustration. Such bias and control circuits are well known for non-volatile memories.
Storage array 1120 contains non-volatile memory cells for storing analog voltages in an analog format. In particular, to write an analog data value to a selected memory cell in storage array 1120, a user provides a data signal Ain and an address signal to memory 1100 through I/O ports (not shown). A user can also provide a conversion select signal CSEL (not shown for simplicity), such as described above with reference to FIGS. 9A and 9B, to select a type of conversion and corresponding row in the conversion array 1110. The write process then proceeds in three steps: an analog-to-digital conversion step, a digital-to-analog conversion step, and a programming step. The combination of the analog-to-digital conversion and the digital-to-analog conversion implements a desired transformation of analog input signal Ain to analog output signal Aout, as described above. During the programming step, the threshold voltage of the selected memory cell is written to the same voltage as signal Aout.
For the analog-to-analog conversion, the address signal or the conversion select signal CSEL identify a selected reference cell in conversion array 1110. Signals ROWADDR and COLADDR are applied to row decoder 1150 and column decoder 1140 through respective multiplexers 1170 and 1114 to select the row and column, respectively, containing the desired reference cell. ROWADDR and COLADDR are selected from either the input address signal Din or the output signal Dout of the encoder 830, with ROWADDR also depending on the type of conversion desired (i.e., CSEL, not shown) within conversion array 1110. After conversion to the desired analog signal Aout, such as described in detail above, signal Aout can then be stored in designated memory cells in storage array 1120.
For the programming step, the input address signal Din identifies a selected memory cell in storage array 1120. To make the existence of conversion array 1110 transparent, row address ROWADDR includes a separate bit which memory 1100 sets when accessing conversion array 1110. Accordingly, the input address signal need not account for the existence or size of conversion array 1110. Signals ROWADDR and COLADDR are derived from the input address signal and respectively applied to row decoder 1150 and column decoder 1140 to select a row line and a column line in array 1130. Row decoder 1150 and column decoder 1140 then apply signals to the selected row and column lines to program the selected memory cell to a threshold voltage equal to or having a one-to-one correspondence with analog signal Aout through a multiplexer 1160. Many write processes are known and suitable for programming the selected memory cell to the target threshold voltage.
An exemplary write process performs a series of programming cycles and verify cycles on the selected memory cell. During a programming cycle, column decoder 1140 applies a high voltage (typically 5-6 volts) to the selected column line, and row decoder 1150 applies a high voltage Vpp (8-12 volts) to the selected row line. Row decoder 1150 generates the row line voltage (not shown) at a level that is linearly or otherwise dependent on analog signal Aout so that programming cycles for a higher target voltage Aout use a higher programming voltage. Verify cycles determine whether the threshold voltage of the selected memory cell has reached the target voltage Aout. This can be achieved by applying voltage Vvfy, which is proportional to Aout, to the selected row line, applying a voltage of approximately 1.5 volts to the selected column line, and sensing whether the selected memory cell conducts. The selected memory cell stops conducting upon reaching the target threshold voltage, and the write operation is terminated.
The stored analog voltages can be accessed through a threshold voltage determination. For threshold voltage determination, signals COLADDR and ROWADDR identify a selected column line and a selected row line for a memory cell in storage array 1120. Column decoder 1140 biases the selected row line to a positive voltage. Row decoder 1150 and ramp circuit 842 ramp the voltage on the selected row line, and the sense amplifier 944 coupled to the selected column line triggers sample-and-hold circuit 848 when the selected memory cell begins to conduct. At this point, analog signal Aout has a voltage about equal to or having a one-to-one correspondence with the threshold voltage of the selected memory cell, and the determination step is complete. Signal Aout can then be used for further processing or transmission or can be converted again to another format, such as reconversion back to the original signal format.
For another conversion, signal ROWADDR identifies a conversion according to the conversion select signal (not shown) and causes row decoder 1150 to select a row line in conversion array 1110 for implementing the desired conversion. For example, with playback of audio signals, as discussed above, the desired conversion can be an inverse of the original logarithmic conversion. In this case, signal ROWADDR selects the row containing memory cells programmed with threshold voltages that are the inverse of the original conversion array. Thus, multiple sequential conversions can be performed with a single large memory array. This technique allows multiple levels of encryption on a signal, which may be desirable in some applications as opposed to a single encryption or conversion.
As described above, memory 1100 has a single memory array which is partitioned into conversion array 1110 and storage array 1120. Alternatively, conversion array 1110 and storage array 1120 can be separate structures to allow simultaneous access of arrays 1110 and 1120. With separate conversion and storage arrays, a series of read operations or a series of write operations can be pipelined to provide a higher data flow rate, such as described in commonly-owned U.S. Pat. No. 5,680,341, entitled "PIPELINED RECORD AND PLAYBACK FOR ANALOG NON-VOLATILE MEMORY" to Wong et al., which is incorporated by reference in its entirety. For example, for writing a series of multi-bit values, the programming step for each write in the series can be performed simultaneously with the conversion step for the next write in the series. Thus, the total time for the series of writes is approximately equal to the product of the number of values and the time required for the programming step, and the throughput of the memory is increased.
However, with analog-to-digital and/or digital-to-analog conversion, operation of the memory systems primarily involves reading the memory cells, which is much faster than writing to the memory cells, i.e., reading typically requires less than 1 μsec. Thus, the operation of the memory systems are slowed when performing non-reading operations, such as when a new conversion is desired, which requires writing or programming new threshold voltages in the memory cells. Because such situations arise are much less frequently than an analog-to-digital or digital-to-analog conversion, these converters have very high operational speeds.
Other than analog-to-analog conversion and the storage of analog/multi-level data, memory system 1100 can also be used to store conventional digital data. For example, signals Ain and Aout have two discrete levels, high and low, instead of a range of analog values. Additionally, memory system 1100 can be used as a conventional analog-to-digital or digital-to-analog converter provided that the conversion array includes linear rather than non-linear conversion tables.
Although the invention has been described with reference to particular embodiments, the description is only an example of the invention's application and should not be taken as a limitation. For example, although the above embodiments describe encoding the binary outputs T0 to Tx from sense circuits to obtain a digital output, these binary outputs can be used to directly select the desired reference cells for the subsequent analog conversion. Thus, various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as defined by the following claims.
