Presentations & publications

Conference Presentation

1986

CMOS Erasable Programmable Logic with Zero Standby Power

Sau Wong · Hock So · Chuan Hung · Jung Ou

1986 IEEE International Solid-State Circuits Conference (ISSCC) — February 19–21, 1986 · Anaheim, CA

Programmable logic ICs with a complexity of up to 2000 gates will be reported. An input transition detector powers up the circuits and differential logic in the critical speed paths affords a 25ns delay.

Journal Article

1986

Novel Circuit Techniques for Zero-Power 25ns CMOS Erasable Programmable Logic Devices (EPLD's)

S.C. Wong · H.C. So · C.Y. Hung · J.H. Ou

IEEE Journal of Solid-State Circuits — October 1986 · Volume 21, No. 5, pp. 766–774

A family of CMOS erasable programmable logic devices (EPLDs) is described with emphasis on the state-of-the-art chip architecture and circuit design techniques. The main features of this family of EPLDs include zero standby power, high-speed operation, flip-flop reconfigurability, small chip size, and high reliability. A novel input-transition-detection circuit allows the chip to consume no power during standby and yet wakes the chip up with minimum delay. Basic architectural differences between EPLDs and EPROM are discussed that require extra design considerations to achieve an optimal speed path through the array. A direct-drive technique is used in the transistor-transistor logic buffer and flip-flop circuits to improve speed, layout area, and chip organization.

Conference Presentation

1989

A 5000-gate CMOS EPLD with Multiple Logic and Interconnect Arrays

Sau C. Wong · Hock C. So · Jung H. Ou · John Costello

1989 IEEE Custom Integrated Circuits Conference (CICC) — May 15–18, 1989 · San Diego, CA

A description is given of a CMOS electrically programmable logic device (EPLD) with over 220000 programmable elements organized into multiple logic array blocks (LABs) that communicate through a separate programmable interconnect array. Redundancy, for the first time ever in programmable logic devices, is implemented in both arrays to improve yield. Devices of different sizes can be easily constructed by varying the number of LABs and/or macrocells within one LAB. A 2X improvement in yield has been observed.

Oral History

2009

Altera EP300 Design & Development Oral History Panel

Yiu-Fai Chan · Robert Frankovich · Robert Hartman · Clive McCarthy · Don (Sau-Ching) Wong

Computer History Museum, Mountain View, CA — Moderated by Stephen Smith · Recorded August 20, 2009

Five engineers involved in the founding of Altera discuss the design and development of the EP300, the company's first product and the first reprogrammable logic device — from the company's formation and hand-done design and verification work to shipping the product with a single mask turn.