Periodic refresh operations for non-volatile multiple-bit-per-cell memory

Abstract

A multi-bit-per-cell non-volatile memory performs periodic refresh operations. The refresh operations can be timed according to a maximum tolerable drift for threshold voltages representing the data and an expected rate of drift of the threshold voltage. The refresh operation can move data to different physical storage locations and extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.