By way of introduction, a schematic diagram is shown in FIG. 1 of a well known prior art EPROM switching circuit which can be used in accordance with the present invention to generate a control signal. For purposes of this discussion an N-channel transistor is representationally shown, it being understood that a P-channel device could similarly be used. Furthermore, it is to be understood that the term EPROM is intended to include both EPROM and EEPROM devices. In FIG. 1, the EPROM transistor 10 has a gate 12 connected to an input terminal 14, a source 16 connected to circuit ground, and a drain 18 connected to an output node 20 and through a load resistor 22 to a supply voltage Vcc at a terminal 24.
If it is assumed that a floating gate 13 of the transistor is initially unprogrammed then the transistor can be expected to work as follows. Whenever a positive voltage greater than a certain threshold voltage (Vt) is applied to the control gate 12, a channel will be induced under the gate region of the transistor, which allows current to flow between the drain region and the source region. In a typical N-channenl floating gate device Vt is approximately 1.5 volts. The signals which are typically applied to a control gate are normally between 0 volts and 5 volts. With no input voltage applied to terminal 14, it will be appreciated that transistor 10 will be in a nonconducting or OFF state and node 20 will be pulled up through load element 22 to Vcc and thus be in a logic 1 state.
If on the other hand, an input voltage Vcc (nominally +5 volts) is applied to the gate 12, transistor 10 will be caused to conduct (turn ON) creating a current path between terminal 24 and circuit ground through load element 22. The load element 22 and transistor 10 are designed such that the control signal appearing at node 20, with transistor 10 conducting, will be less than the threshold voltage of a circuit to be controlled by the control signal. Thus, with transistor 10 turned ON, node 20 will be pulled toward ground potential and will thus be at a logic 0 state.
The effective threshold of transistor 10 will be changed by causing charges to be trapped on the floating gate 13. More particularly, electrons can be caused to flow to the floating gate 13 by applying a high voltage (typically 21 volts) to the control gate and the drain (by means not illustrated). When the high voltage is removed, charges will remain trapped on the floating gate 13 and cause the effective threshold of the device to be increased to a value greater than the voltage which would normally be applied to the control gate 12. The application of such high voltage and the subsequent charge trapping on the floating gate 13 is called "programming".
After transistor 10 has been programmed, if a 5 volt signal such as Vcc is applied to gate 12 no channel will be created between the source and drain, and no current will flow therebetween. Accordingly, transistor 10 will remain in its OFF condition causing node 20 to be pulled up to Vcc through load element 22. The control signal developed at node 20 will thus be greater than the threshold voltage of the circuit to be controlled, and will thus be considered to be at a logic 1 state.
The EPROM device can thus be thought of as a programmable switch. In the unprogrammed state, the switch opens and closes in response to the application of 0 volts or 5 volts, respectively, to the control gate 12. On the other hand, in the programmed state the switch will always be open regardless of whether 0 volts or 5 volts is applied to control gate 12. Under normal environmental conditions charges will stay trapped on the floating gate for very long periods of time, typically greater than 10 years.
Referring now to FIG. 2. of the drawing. A generalized block diagram is presented representatively showing a macrocell 28 including an architectural control circuit 30 connected to logic or other circuitry 32 to be controlled. In accordance with the present invention, circuit 30 is comprised of an EPROM (or EEPROM) transistor 34, Read and Write Control subcircuitry 36, and sense subcircuitry 38. Typically, the drain 40 and gate 42 of transistor 34 will be controlled by the Read and Write Control circuit 36, while the source 44 of the transistor is tied to ground. The sense circuit 38 couples the drain 40 to the circuitry 32 to be controlled. Furthermore, circuit 38 "senses" the programmed or unprogrammed state of transistor 34 and produces a corresponding logic 1 or logic 0 output signal at 46 which is used to control one or more subcircuits of circuitry 32.
Although illustrated as a single EPROM architecture control circuit 30, in the usual case a plurality of such circuits are combined to allow selective characterization of the operation of a particular logic or other circuit such as that depicted at 32. It will be appreciated, however, that the intended function of the several architecture control circuits is to input logic 1's and 0's to particular gates of the controlled circuit thus allowing the operational characteristics of such circuit to be tailored to fit a particular application.
Turning now to FIG. 3 of the drawing, a detailed schematic of an embodiment of the present invention is shown in an application in which EPROM control circuits are used to control a Transmission Gate Multiplexer circuit. In this embodiment, three Architectural Control circuits 30, 30' and 30" are shown in combination with multiplexing circuitry generally indicated at 32, which is in turn used to control the signal communication between the output, feedback and I/O of an AND-OR Logic Array 40. The overall architectural control system includes the three control circuits 30, 30' and 30" which respectively include the Read and Write Control subcircuits 36, 36' and 36" the EPROMs 34, 34' and 34" and the sense subcircuits 38, 38' and 38".
As mentioned, the circuitry 32 to be controlled is a three input transmission gate multiplexor consisting of switching transistors 50, 52 and 54 which forms part of an AND-OR array macrocell of the type disclosed in co-pending U.S. patent application Ser. No. 06/607,018 filed May 3, 1984 and assigned to the assignee of the present application. As illustrated, transistor 50 selectively connects the output of AND-OR array 40 to an amplifier 56 in a feedback loop, transistor 52 selectively connects the output of a D-flip-flop to amplifier 56, and transistor 54 selectively connects I/O pad 64 to amplifier 56 via an I/O driver 62. It will be appreciated that by means of the control circuits 30, any combination of the gates 50-54 may be actuated to specially configure the illustrated array.
Referring now to circuit 30, observe that control circuit 36 is comprised of a P-channel load transistor 102, three pull-down transistors 103, 104 and 105, the gates of which are connected to address terminals 121, 122, and 123, a blocking transistor 106, a level shifter or translator circuit consisting of three P-channel transistors 107, 108, and 109, and two N-channel transistors 110 and 111, the output of the translator circuit being connected to the gate of EPROM 34. Circuit 36 also includes a P-channel transistor 113 and an N-channel transistor 114 the gates which are connected to a program data input terminal 112 and invert an input applied thereto, and a transistor 115 the gate of which is connected to the drains of transistors 113 and 114. The source 116 of transistor 115 is connected to the drain of EPROM 34.
Sense circuit 38 includes a gating transistor 132, a P-channel load device 134 and a Schmidt Trigger Circuit 135 including a P-channel transistor 136 and N-channel transistors 137-139. The output node 141 of Schmidt trigger circuit 135 is coupled to the gate of transistor 50 of the multiplexing circuit 32.
Similarly, the other two (or more) control circuits consisting of read/write circuits 36' and 36", EPROM transistors 34' and 34" and sense circuits 38' and 38" are respectively coupled to the gates of transistors 52 and 54. It should be understood that each of the circuits 36, 36' and 36" share a common data line 112 and common address lines 121-123. The use of inverters to interface appropriate address lines to 36' and 36" allow selection of a particular one of the EPROMs 34', 34" to be programmed by the data signal input on the program data input line.
Operation of the illustrated circuit may be explained as follows:
Assume initially that the EPROM transistors 34, 34' and 34" are in their erased state and it is desired to write a value to the floating gates. For purposes of this discussion a description of the "Write" operation for only transistor 34 will be given although such operations for 34' and 34" will be similar. During writing, the Vpp/Vcc line is switched to Vpp (typically 21 volts). Transistor 102 serves as a load transistor and transistors 103, 104 and 105 are pull down transistors making up a 3 input NOR gate. If the address inputs 121, 122, and 123 are all logic 0 then the output of the NOR gate at node 101 will be a logic 1. With Vcc at the gate of transistor 106 it will be rendered conductive and the logic 1 will be passed to node 117. Because the gate of transistor 106 is connected to Vcc, the initial node voltage at 117 will be Vcc-Vt, or approximately 4 volts. This will be high enough to turn transistor 110 ON, but not enough to turn P-channel transistor 108 OFF.
With transistor 110 ON, node 118 begins to be pulled toward ground. This turns P-channel transistor 107 ON and pulls node 117 toward Vpp which turns transistor 108 fully OFF. With node 118 at ground, N-channel transistor 111 is OFF and P-channel transistor 109 is ON causing node 119 to be pulled up to Vpp which is the desired programming gate voltage for EPROM transistor 38. Line 112 contains the data to be programmed. If the data on line 112 is a logic 0, then transistor 115 will be turned ON and the EPROM transistor 34 will be programmed as the drain 133 of transistor 34 is pulled to Vpp through N-channel transistor 115. If the signal input on line 112 is a logic 1 transistor 115 will remain OFF and the EPROM transistor will not be programmed.
Once the EPROM transistor 34 is programmed, it can be sensed by Sense circuit 38. During the normal operation (after programming), line 112 is forced to a logic 1, Vpp/Vcc is forced to Vcc and lines 121, 122 and 123 are forced to logic 0, thus node 119 will be at a Vcc level.
The Sense circuit works as follows: First, assume that transistor 34 is in its erased state. With 5 volts applied to its gate it will be turned ON. P-channel transistor 134 acts as a load element for transistor 34 through pass gate transistor 132. The sizes of transistors 132, 134 and EPROM 34 are chosen such that node 40 will be near ground (logic 0) when EPROM 34 is in its erased state. This level is sensed by Schmidt trigger circuit 135. A logic 0 on node 140 produces a logic 1 on node 141. Thus, an erased EPROM (unprogrammed) transistor will be sensed as a logic 1.
Next, assume that the EPROM 34 has been programmed and is in its OFF state. Then with 5 volts on its gate it will still be in an OFF configuration. This will be sensed by the Schmidt trigger and a logic 0 will be output at 141. Thus, a programmed EPROM transistor produces a logic 0 at node 141.
In a similar manner, EPROM transistors 34' and 34" can be programmed by their respective Read/Write Control circuits 36' and 36". Having programmed EPROM transistors 34 34' and 34", the control signals developed on lines 142, 242 and 342 are used to control the transmission multiplexer (TMUX). Typically, in a TMUX only one path is active. For example, assume the gate of transistor 50 is at a logic 1, and the gates of transistors 52 and 54 are at logic 0, then data from the AND/OR Logic Array 40 will be passed via line 42 through transistor 50 to node 44 where it will be amplified by the multiplex amplifier 56 and (in this illustration) passed back to the AND/OR Array 40. If transistor 52 had been selected (rather than 50) than data from the D flip-flop 60 would have been fed back to the AND/OR Array 40. If transistor 54 had been selected, then I/O pad data would have been passed through amplifier 56 to the AND/OR Array 40.
Many other circuits can also be controlled by EPROM architecture control circuits of the type described. For example, FIG. 4 shows an inversion control circuit (of the type disclosed by Brickman et al in "Programmable Logic Array Enhancement", IBM Tech. Disclosure Bulletin, p. 583, Vol. 19, No. 2, July 1976). in which an EPROM architecture control circuit 70 in accordance with the present invention generates a control signal C on a control line 72. By applying the control signal C to one input of an exclusive NOR gate 74, the output signal Y at 76 will be either the same as, or the logical inversion of, the logic signal I input at 78. The following truth table illustrates the application:
It will thus be appreciated that when C=0, Y=I, and when C=1, Y=I.
FIG. 5 illustrates a digital multiplexer in which a plurality of EPROM architecture control circuits 80, 81 and 82, provide control signals C1, C2, . . . Cn for the multiplexing circuitry consisting of AND gates 83, 84 and 85, the outputs of which are fed into an OR gate 86. The output Y of OR gate 86 will be the logical OR of all signals I1, I2, . . . . In whose control signals C1, C2 . . . Cn are set to logic 1. The logic equation for this circuit is:
By way of example, if C1=0, C2=1, and C3 through Cn=0, then Y=I2.
In FIG. 6 another version of a multiplexer circuit is shown wherein pass gates T1, T2 . . . Tn are controlled by EPROM architecture control circuits 87, 88, and 89. In this type of circuit, normally referred to as a Transmission Gate Multiplexer, only one of the pass gates can be enabled or a conflict will exist at node 90 and the output signal Y will be indeterminate. Assuming only one control signal, for example C1, is at a logic 1 state then the circuit works as follows: Transistor T1 is turned ON and transistors T2 . . . Tn are turned OFF. Signal DS1 will then be passed to node 90. If DS1 is a logic 0, then node 90, will also be pulled to logic 0, and the output 91 of inverter 92 will be at logic 1, which turns OFF transistor TP1. The output Y from inverter 93 will thus be at logic 0.
Next, assume DS1 goes to a logic 1. Initially node 90 can only go as high as Vcc-Vt (assuming the logic 1 level of C1 is Vcc). Inverter 92 is designed such that Vcc-Vt is enough to begin pulling node 94 low. This will turn Tp1 ON and pull node 90 to Vcc. Output Y will then go to logic 1 in response to a logic 0 at node 94.
In FIG. 7 a special case of the transmission gate multiplexer is shown in which an EPROM architectural control circuit 95 is used to accomplish inversion control. In this circuit, two transmission gates T1 and T2 are controlled by an EPROM architecture control bit C. Depending upon the state of the invert control line 96, either T1 will be ON and T2 will be OFF or T1 will be OFF and T2 will be ON. If T1 is ON, the logic signal Z will be passed to node 97 and thereafter through the multiplexer amplifier (as in FIG. 6) to the output 98. In this case, the output 98 will have the same logical values as input Z. If, on the other hand, T2 is ON, the logic signal Z will be inverted by the inverter gate 99 and passed to node 97 and thence to the output 98. In this case, output 98 will be the logical complement of the input signal Z. Thus, the circuit shown in FIG. 7 acts as a programmable inverter under control of an EPROM control bit.
Although the present invention has been described above with regard to a particular preferred embodiment which can be utilized as the control means for several different types of circuits, it is contemplated that other circuits and embodiments will become apparent to those skilled in the art after having read the above disclosure. It is therefore intended that the following claims be interpreted as covering all such circuits and embodiments as fall within the true spirit and scope of the invention.
